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The LME49810 contains Baker Clamps on the output driver transistors. The Baker Clamp is essentially a configuration of diodes connected around a Bipolar Junction Transistor which prevent the Collector-Emitter junction from saturating (turning on as hard as possible). Recovery from saturation takes a finite amount of time, which can introduce some undesireable artefacts into the amplifier chain.
The best description I have found of the Baker Clamp is in "Rectifier Applications Handbook", Revision 2, November 2001, by ON Semiconductor, part number HB214/D. This publication is Copyright 2001 SCILLC. Pages 175 - 177 of the section "Drive Circuits for Bipolar Power Transistors" are reproduced from Chapter 11 "Power Electronic Circuits" for the purposes of fair research.
The storage time associated with the turn-off of bipolar transistors has always been a problem for circuit designers. Allowance must be made for worst-case storage time or disastrous events may occur. Such allowance lowers efficiency because it shortens the time available to deliver power pulses, which in turn raises the peak current. Unfortunately, storage time varies considerably with the values of IC and IBI prior to turn-off and with the amplitude and waveshape of IB2. A technique developed many years ago by R.H. Baker is shown in Figure 171. It reduces and stabilizes storage time as operating conditions vary.
Figure 171. Baker Clamp Configuration
Circuit operation is as follows. When a positive pulse is applied to an initially off transistor, forward current flows through DB into the base of the transistor, turning it on. The voltage at the input is set at two diode drops, approximately 1.5 V. As collector current builds up and collector voltage drops, diode DF starts to conduct and keeps VCE from falling below about 0.8 V. This action prevents the bipolar operating point from entering the hard saturation region and theoretically eliminates storage time since the collector-base junction is not reverse biased. Diode DF acts as a current-regulating feedback element, setting the base current to the amount required by the transistor at a particular collector current and on-state voltage. Current at the input which exceeds this base current (i.e., excess current) is shunted into the collector circuit by diode DF. When the input pulse goes negative, reverse current is drawn from the base through diode DR in parallel with diode DB until its stored charge is depleted. Resistor R is present mainly for noise immunity; it also establishes a small reverse off-state voltage at the base if the input level remains negative.
The Baker Clamp provides the expected results for low-voltage bipolar transistors - that is, storage time becomes negligible and fall time is not affected. However, high voltage power transistors exhibit a quasi-saturation region caused by stored charge in their wide, high resistivity collector region. When operated in quasi-saturation, some storage time still occurs. It is possible to move operation out of the quasi-saturation region by stacking additional diodes in series with DB, but the on-state loss becomes unacceptably high.
It might seem that the Baker Clamp is not particularly effective with high-voltage transistors; however, operation in hard saturation causes anomalous fall time behavior, while fall time behavior is more theoretical if operation extends only into the quasi-saturation region. To show the effectiveness of a Baker Clamp  the test circuit of Figure 172(a) was used. Transistors Q1 and Q2 are alternately turned on to provide IB1 and IB2 to the power switch. The load inductor, diode, and capacitor simulate a flyback converter load. A sketch of the waveforms observed are shown in Figure 172(b). When II is first applied, it is delivered solely to the transistor base. Current builds up slowly in the inductor but its high impedance allows collector voltage to drop quickly. Diode DF conducts, shunting the excess base current into the collector of the power switch. As collector current (ICT) rises, base current (IB1) drops and maintains the value IC/hFE as collector current ramps toward its peak, which is established by the pulse width of II.
Figure 172. Baker Clamp Circuit for Evaluating High-Voltage Transistors: (a) Test Circuit; (b) Waveforms
The most interesting results occur with a fixed base drive and a variable collector current, a common situation in a switching power supply. The effect upon storage time is shown in Figure 173. Note that use of the Baker Clamp has achieved a remarkable reduction in storage time at low collector currents and its value is somewhat independent of collector current. Improvement in fall time is even more spectacular as shown in Figure 174. The trade-off made for the improved switching performance is an increased on-state voltage. It is typically 0.3 V in hard saturation and 0.9 V with the Baker clamp.
Figure 173. Storage Time with Fixed Drive in a Baker Clamp Circuit
Figure 174. Fall Time with Fixed Drive in a Baker Clamp Circuit
Not all transistors will exhibit the behavior illustrated in Figures 173 and 174, and data of this nature rarely appears on manufacturer’s data sheets. Consequently, it is advisable to test transistors in a circuit similar to Figure 172 to determine if the improvement in switching losses more than offsets the additional on-state losses associated with the Baker Clamp.
Selection of the diodes deserves critical attention. The collector feedback diode DF needs to be able to block the voltage applied to the collector of the transistor. Its stored charge should be low enough that the diode recovers during the storage time of the transistor. Otherwise, it will play a role in the turn-off process, affecting both storage and fall time. Finding the right diode may not be easy since stored charge is not often specified and conditions for reverse recovery specifications do not approximate those in a Baker Clamp circuit. As a rough rule of thumb, the specified reverse recovery time should be under a quarter of the specified storage time of the transistor. Testing a number of samples with a current probe in series with diode DF will normally be necessary to be sure that an adequate margin exists between diode recovery time and transistor storage time. A slow forward recovery time is actually beneficial. The delay allows the spike of current from II to persist longer, thus reducing turn-on loss. Fortunately, slow forward recovery is a characteristic of high-voltage diodes, regardless of their stored-charge behavior.
On the other hand, fast forward recovery is important for diode DB, unless a peaking capacitor is placed in parallel with it. A low-voltage diode provides fast forward recovery. A large area diode also may provide sufficient peaking capacitance. Slow reverse recovery is an advantage. The stored charge will hold the anode positive during the turn-off phase, thereby increasing the current available from the negative voltage source. Often diode DR is omitted; the circuit then depends upon the stored charge in diode DB to exceed the stored charge in the transistor, thereby providing a current path for IB2 until the transistor turns off. Diode DR also has non-critical requirements. It is used simply to apply reverse current (IB2) when VI is derived from a scheme which drives VI negative.